The first screenshot was taken after 40 seconds of running the game without pressing any button. The second screenshot was taken after 120 seconds, after attempting to start the game by repeatedly pressing Start and A. 2790 out of 2791 games passed.
Games incompatible with the Game Boy Color are tested in DMG mode
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 40 to ff44 (HW Register)
40 Seconds log: Wrote 80 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 26 to f008 (RAM Mirror) Wrote 37 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wrote 00 to f011 (RAM Mirror) Wrote 00 to f012 (RAM Mirror) Wrote 00 to f013 (RAM Mirror) Wrote 00 to f014 (RAM Mirror) Wrote 00 to f015 (RAM Mirror) Wrote 00 to f016 (RAM Mirror) Wr...) Wrote d9 to f3a6 (RAM Mirror) Wrote d9 to f3a7 (RAM Mirror) Wrote 00 to f3a8 (RAM Mirror) Wrote 5a to f3a9 (RAM Mirror) Wrote 5a to f3aa (RAM Mirror) Wrote 00 to f3ab (RAM Mirror) Wrote 00 to f3ac (RAM Mirror) Wrote 00 to f3ad (RAM Mirror) Wrote 00 to f3ae (RAM Mirror) Wrote 00 to f3af (RAM Mirror) Wrote d9 to f3b0 (RAM Mirror) Wrote 00 to f3b1 (RAM Mirror) Wrote 00 to f3b2 (RAM Mirror) Wrote 00 to f3b3 (RAM Mirror) Wrote 00 to f3b4 (RAM Mirror) Wrote 00 to f3b5 (RAM Mirror) Wrote d9 to f3b6 (RAM Mirror) Start attempt log: Wrote 80 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 26 to f008 (RAM Mirror) Wrote 37 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wrote 00 to f011 (RAM Mirror) Wrote 00 to f012 (RAM Mirror) Wrote 00 to f013 (RAM Mirror) Wrote 00 to f014 (RAM Mirror) Wrote 00 to f015 (RAM Mirror) Wrote 00 to f016 (RAM Mirror) Wr...) Wrote d9 to f3a6 (RAM Mirror) Wrote d9 to f3a7 (RAM Mirror) Wrote 00 to f3a8 (RAM Mirror) Wrote 5a to f3a9 (RAM Mirror) Wrote 5a to f3aa (RAM Mirror) Wrote 00 to f3ab (RAM Mirror) Wrote 00 to f3ac (RAM Mirror) Wrote 00 to f3ad (RAM Mirror) Wrote 00 to f3ae (RAM Mirror) Wrote 00 to f3af (RAM Mirror) Wrote d9 to f3b0 (RAM Mirror) Wrote 00 to f3b1 (RAM Mirror) Wrote 00 to f3b2 (RAM Mirror) Wrote 00 to f3b3 (RAM Mirror) Wrote 00 to f3b4 (RAM Mirror) Wrote 00 to f3b5 (RAM Mirror) Wrote d9 to f3b6 (RAM Mirror)
40 Seconds log: Wrote 02 to ff60 (HW Register) Start attempt log: Wrote 02 to ff60 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08...3 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register)
40 Seconds log: ROM header reports no MBC, but file size is over 32Kb. Assuming cartridge uses MBC3. Wrote 03 to ff60 (HW Register) Start attempt log: ROM header reports no MBC, but file size is over 32Kb. Assuming cartridge uses MBC3. Wrote 03 to ff60 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: ROM header reports no RAM, but also reports a non-zero RAM size. Assuming cartridge has RAM. Start attempt log: ROM header reports no RAM, but also reports a non-zero RAM size. Assuming cartridge has RAM.
Start attempt log: Wrote 00 to f01f (RAM Mirror) Wrote 00 to f03f (RAM Mirror) Wrote 00 to f05f (RAM Mirror) Wrote 00 to f07f (RAM Mirror) Wrote 00 to f09f (RAM Mirror) Wrote ff to f0bf (RAM Mirror) Wrote ff to f0df (RAM Mirror) Wrote ff to f0ff (RAM Mirror) Wrote ff to f11f (RAM Mirror) Wrote ff to f13f (RAM Mirror) Wrote ff to f15f (RAM Mirror) Wrote ff to f17f (RAM Mirror) Wrote ff to f19f (RAM Mirror) Wrote ff to f1bf (RAM Mirror) Wrote ff to f1df (RAM Mirror) Wrote ff to f1ff (RAM Mirror) Wrote ff to f21f (RAM Mirror) Wr...) Wrote ff to f5ff (RAM Mirror) Wrote 00 to f61f (RAM Mirror) Wrote 00 to f63f (RAM Mirror) Wrote 00 to f65f (RAM Mirror) Wrote 00 to f67f (RAM Mirror) Wrote ff to f69f (RAM Mirror) Wrote 00 to f6bf (RAM Mirror) Wrote 00 to f6df (RAM Mirror) Wrote 00 to f6ff (RAM Mirror) Wrote 00 to f71f (RAM Mirror) Wrote ff to f73f (RAM Mirror) Wrote ff to f75f (RAM Mirror) Wrote 00 to f77f (RAM Mirror) Wrote 00 to f79f (RAM Mirror) Wrote 00 to f7bf (RAM Mirror) Wrote 00 to f7df (RAM Mirror) Wrote 00 to f7ff (RAM Mirror)
40 Seconds log: Wrote 02 to ff60 (HW Register) Start attempt log: Wrote 02 to ff60 (HW Register) Wrote 02 to ff60 (HW Register)
40 Seconds log: Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Start attempt log: Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44...4 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 08 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44...4 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Start attempt log: Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 03 to ff44 (HW Register) Wrote 08 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44...4 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 02 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 01 to ff44 (HW Register) Wrote 02 to ff44 (HW Register) Wrote 01 to ff44 (HW Register)
Start attempt log: Wrote 01 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 10 to ff44 (HW Register) Start attempt log: Wrote 10 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Start attempt log: Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e...3 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register)
40 Seconds log: Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Start attempt log: Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e...3 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff03 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported...ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
Start attempt log: Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c...c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register)
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported...ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to f000 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 00 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 00 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 00 to f008 (RAM Mirror) Wrote 00 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wr...) Wrote 00 to fdef (RAM Mirror) Wrote 00 to fdf0 (RAM Mirror) Wrote 00 to fdf1 (RAM Mirror) Wrote 00 to fdf2 (RAM Mirror) Wrote 00 to fdf3 (RAM Mirror) Wrote 00 to fdf4 (RAM Mirror) Wrote 00 to fdf5 (RAM Mirror) Wrote 00 to fdf6 (RAM Mirror) Wrote 00 to fdf7 (RAM Mirror) Wrote 00 to fdf8 (RAM Mirror) Wrote 00 to fdf9 (RAM Mirror) Wrote 00 to fdfa (RAM Mirror) Wrote 00 to fdfb (RAM Mirror) Wrote 00 to fdfc (RAM Mirror) Wrote 00 to fdfd (RAM Mirror) Wrote 00 to fdfe (RAM Mirror) Wrote 00 to fdff (RAM Mirror) Start attempt log: Wrote 00 to f000 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 00 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 00 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 00 to f008 (RAM Mirror) Wrote 00 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wr...) Wrote 00 to fdef (RAM Mirror) Wrote 00 to fdf0 (RAM Mirror) Wrote 00 to fdf1 (RAM Mirror) Wrote 00 to fdf2 (RAM Mirror) Wrote 00 to fdf3 (RAM Mirror) Wrote 00 to fdf4 (RAM Mirror) Wrote 00 to fdf5 (RAM Mirror) Wrote 00 to fdf6 (RAM Mirror) Wrote 00 to fdf7 (RAM Mirror) Wrote 00 to fdf8 (RAM Mirror) Wrote 00 to fdf9 (RAM Mirror) Wrote 00 to fdfa (RAM Mirror) Wrote 00 to fdfb (RAM Mirror) Wrote 00 to fdfc (RAM Mirror) Wrote 00 to fdfd (RAM Mirror) Wrote 00 to fdfe (RAM Mirror) Wrote 00 to fdff (RAM Mirror)
Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to f000 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 00 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 00 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 00 to f008 (RAM Mirror) Wrote 00 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wr...) Wrote 00 to fc15 (RAM Mirror) Wrote 00 to fc16 (RAM Mirror) Wrote 00 to fc17 (RAM Mirror) Wrote 00 to fc18 (RAM Mirror) Wrote 00 to fc19 (RAM Mirror) Wrote 00 to fc1a (RAM Mirror) Wrote 00 to fc1b (RAM Mirror) Wrote 00 to fc1c (RAM Mirror) Wrote 00 to fc1d (RAM Mirror) Wrote 00 to fc1e (RAM Mirror) Wrote 00 to fc1f (RAM Mirror) Wrote 00 to fc20 (RAM Mirror) Wrote 00 to fc21 (RAM Mirror) Wrote 00 to fc22 (RAM Mirror) Wrote 00 to fc23 (RAM Mirror) Wrote 00 to fc24 (RAM Mirror) Wrote 00 to fc25 (RAM Mirror) Start attempt log: Wrote 00 to f000 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 00 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 00 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 00 to f008 (RAM Mirror) Wrote 00 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wr...) Wrote 00 to fc15 (RAM Mirror) Wrote 00 to fc16 (RAM Mirror) Wrote 00 to fc17 (RAM Mirror) Wrote 00 to fc18 (RAM Mirror) Wrote 00 to fc19 (RAM Mirror) Wrote 00 to fc1a (RAM Mirror) Wrote 00 to fc1b (RAM Mirror) Wrote 00 to fc1c (RAM Mirror) Wrote 00 to fc1d (RAM Mirror) Wrote 00 to fc1e (RAM Mirror) Wrote 00 to fc1f (RAM Mirror) Wrote 00 to fc20 (RAM Mirror) Wrote 00 to fc21 (RAM Mirror) Wrote 00 to fc22 (RAM Mirror) Wrote 00 to fc23 (RAM Mirror) Wrote 00 to fc24 (RAM Mirror) Wrote 00 to fc25 (RAM Mirror)
40 Seconds log: Wrote 00 to f000 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 00 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 00 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 00 to f008 (RAM Mirror) Wrote 00 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wr...) Wrote 00 to fc10 (RAM Mirror) Wrote 00 to fc11 (RAM Mirror) Wrote 00 to fc12 (RAM Mirror) Wrote 00 to fc13 (RAM Mirror) Wrote 00 to fc14 (RAM Mirror) Wrote 00 to fc15 (RAM Mirror) Wrote 00 to fc16 (RAM Mirror) Wrote 00 to fc17 (RAM Mirror) Wrote 00 to fc18 (RAM Mirror) Wrote 00 to fc19 (RAM Mirror) Wrote 00 to fc1a (RAM Mirror) Wrote 00 to fc1b (RAM Mirror) Wrote 00 to fc1c (RAM Mirror) Wrote 00 to fc1d (RAM Mirror) Wrote 00 to fc1e (RAM Mirror) Wrote 00 to fc1f (RAM Mirror) Wrote 00 to fc20 (RAM Mirror) Start attempt log: Wrote 00 to f000 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 00 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 00 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote 00 to f008 (RAM Mirror) Wrote 00 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 00 to f00c (RAM Mirror) Wrote 00 to f00d (RAM Mirror) Wrote 00 to f00e (RAM Mirror) Wrote 00 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wr...) Wrote 00 to fc10 (RAM Mirror) Wrote 00 to fc11 (RAM Mirror) Wrote 00 to fc12 (RAM Mirror) Wrote 00 to fc13 (RAM Mirror) Wrote 00 to fc14 (RAM Mirror) Wrote 00 to fc15 (RAM Mirror) Wrote 00 to fc16 (RAM Mirror) Wrote 00 to fc17 (RAM Mirror) Wrote 00 to fc18 (RAM Mirror) Wrote 00 to fc19 (RAM Mirror) Wrote 00 to fc1a (RAM Mirror) Wrote 00 to fc1b (RAM Mirror) Wrote 00 to fc1c (RAM Mirror) Wrote 00 to fc1d (RAM Mirror) Wrote 00 to fc1e (RAM Mirror) Wrote 00 to fc1f (RAM Mirror) Wrote 00 to fc20 (RAM Mirror)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 80 to ff58 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 80 to ff58 (HW Register) Wrote 80 to ff58 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44...4 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Start attempt log: Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44...4 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register) Wrote dd to ff44 (HW Register)
Start attempt log: Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65...5 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register)
Start attempt log: Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65...5 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register) Wrote ff to ff65 (HW Register)
40 Seconds log: Wrote ff to ff6d (HW Register) Wrote 02 to ff6e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79 (HW Register) Wrote 7f to ff7a (HW Register) Wrote ff to ff6d (HW Register) Wrote 02 to ff6e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79...e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79 (HW Register) Wrote 7f to ff7a (HW Register) Wrote ff to ff6d (HW Register) Wrote 02 to ff6e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79 (HW Register) Wrote 7f to ff7a (HW Register) Start attempt log: Wrote ff to ff6d (HW Register) Wrote 02 to ff6e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79 (HW Register) Wrote 7f to ff7a (HW Register) Wrote ff to ff6d (HW Register) Wrote 02 to ff6e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79...e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79 (HW Register) Wrote 7f to ff7a (HW Register) Wrote ff to ff6d (HW Register) Wrote 02 to ff6e (HW Register) Wrote 5f to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 02 to ff76 (HW Register) Wrote 5f to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote ff to ff79 (HW Register) Wrote 7f to ff7a (HW Register)
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported...ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported...ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 00 to ff0e (HW Register) Start attempt log: Wrote 00 to ff0e (HW Register)
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a...a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Start attempt log: Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a...a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 17 to ff0a (HW Register) Wrote 16 to ff0a (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) W...) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Start attempt log: Wrote 00 to ff7f (HW Register) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror) Wrote e1 to f0b1 (RAM Mirror)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c...c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register)
Start attempt log: Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c...c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Start attempt log: Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote bb to ff7f (HW Register) Start attempt log: Wrote bb to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wr...) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Start attempt log: Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wr...) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror) Wrote 04 to fa0e (RAM Mirror)
Start attempt log: Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register) Wrote fe to ff08 (HW Register) Wrote fe to ff03 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Revertin...PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode.
Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Revertin...PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode.
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a...a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Start attempt log: Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a...a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register) Wrote 18 to ff0a (HW Register) Wrote 16 to ff0a (HW Register)
40 Seconds log: Wrote 00 to ff03 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff0a (HW Register) Start attempt log: Wrote 00 to ff03 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff0a (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register) Wrote 00 to ff7e (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Start attempt log: Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff08 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Cartridge type fd is not yet supported. Game probably stuck with blank screen. Start attempt log: Cartridge type fd is not yet supported. Game probably stuck with blank screen. Screenshots are identical
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
Start attempt log: Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c...c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0c (HW Register)
Start attempt log: Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c...c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register) Wrote ff to ff0c (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. Start attempt log: ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered an APU odd mode, which is currently not tested. ROM triggered a PPU odd mode, which is currently not supported. Reverting to even-mode. ROM triggered an APU odd mode, which is currently not tested.
40 Seconds log: Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Start attempt log: Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register) Wrote 92 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register) Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff03 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff4e (HW Register) Wrote 00 to ff57 (HW Register) Wrote 00 to ff58 (HW Register) Wrote 00 to ff59 (HW Register) Wrote 00 to ff5a (HW Register) Wrote 00 to ff5b (HW Register) Wrote 00 to ff5c (HW Register) Wrote 00 to ff5d...5 (HW Register) Wrote 00 to ff66 (HW Register) Wrote 00 to ff67 (HW Register) Wrote 00 to ff6d (HW Register) Wrote 00 to ff6e (HW Register) Wrote 00 to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 00 to ff76 (HW Register) Wrote 00 to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote 00 to ff79 (HW Register) Wrote 00 to ff7a (HW Register) Wrote 00 to ff7b (HW Register) Wrote 00 to ff7c (HW Register) Wrote 00 to ff7d (HW Register) Wrote 00 to ff7e (HW Register) Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff03 (HW Register) Wrote 00 to ff08 (HW Register) Wrote 00 to ff09 (HW Register) Wrote 00 to ff0a (HW Register) Wrote 00 to ff0b (HW Register) Wrote 00 to ff0c (HW Register) Wrote 00 to ff0d (HW Register) Wrote 00 to ff0e (HW Register) Wrote 00 to ff44 (HW Register) Wrote 00 to ff4e (HW Register) Wrote 00 to ff57 (HW Register) Wrote 00 to ff58 (HW Register) Wrote 00 to ff59 (HW Register) Wrote 00 to ff5a (HW Register) Wrote 00 to ff5b (HW Register) Wrote 00 to ff5c (HW Register) Wrote 00 to ff5d...5 (HW Register) Wrote 00 to ff66 (HW Register) Wrote 00 to ff67 (HW Register) Wrote 00 to ff6d (HW Register) Wrote 00 to ff6e (HW Register) Wrote 00 to ff6f (HW Register) Wrote 00 to ff71 (HW Register) Wrote 00 to ff76 (HW Register) Wrote 00 to ff77 (HW Register) Wrote 00 to ff78 (HW Register) Wrote 00 to ff79 (HW Register) Wrote 00 to ff7a (HW Register) Wrote 00 to ff7b (HW Register) Wrote 00 to ff7c (HW Register) Wrote 00 to ff7d (HW Register) Wrote 00 to ff7e (HW Register) Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 02 to ff60 (HW Register) Wrote 02 to ff60 (HW Register) Start attempt log: Wrote 02 to ff60 (HW Register) Wrote 02 to ff60 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 10 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 80 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote ff to f008 (RAM Mirror) Wrote 01 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 03 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wrote 02 to f011 (RAM Mirror) Wrote 07 to f012 (RAM Mirror) Wrote 01 to f013 (RAM Mirror) Start attempt log: Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 10 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 80 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote ff to f008 (RAM Mirror) Wrote 01 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 03 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wrote 02 to f011 (RAM Mirror) Wrote 07 to f012 (RAM Mirror) Wrote 01 to f013 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wr...) Wrote 01 to f013 (RAM Mirror) Wrote 00 to f001 (RAM Mirror) Wrote 00 to f002 (RAM Mirror) Wrote 10 to f003 (RAM Mirror) Wrote 00 to f004 (RAM Mirror) Wrote 80 to f005 (RAM Mirror) Wrote 00 to f006 (RAM Mirror) Wrote 00 to f007 (RAM Mirror) Wrote ff to f008 (RAM Mirror) Wrote 01 to f009 (RAM Mirror) Wrote 00 to f00a (RAM Mirror) Wrote 00 to f00b (RAM Mirror) Wrote 03 to f00f (RAM Mirror) Wrote 00 to f010 (RAM Mirror) Wrote 02 to f011 (RAM Mirror) Wrote 07 to f012 (RAM Mirror) Wrote 01 to f013 (RAM Mirror)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff0e (HW Register) Start attempt log: Wrote 00 to ff0e (HW Register)
40 Seconds log: Wrote 00 to ff0e (HW Register) Start attempt log: Wrote 00 to ff0e (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)
40 Seconds log: Wrote 00 to ff7f (HW Register) Start attempt log: Wrote 00 to ff7f (HW Register)
40 Seconds log: Wrote 00 to ff44 (HW Register) Start attempt log: Wrote 00 to ff44 (HW Register)